Speaker：Prof. John H Lau

Topic：Fan-Out Wafer-Level Packaging and 2.5D\3D IC Integration

Location：Academic Hall on the third floor of the new No. 9 Teaching Building, School of Power and Mechanical Engineering, WHU

Time：9:00 a.m., Saturday, January 14th^,2017

Organizer：School of Power and Mechanical Engineering, WHU

Welcome to attend the lecture!

 

ABSTRACT

      Recent advances in, e.g., fan-out wafer/panel level packaging (TSMC’s InFO-WLP and Fraunhofer IZM’s FO-PLP), 3D IC packaging (TSMC’s InFO_PoP vs. Samsung’s ePoP), 3D IC integration (Hynix/Samsung’s HBM for AMD/NVIDIA’s GPU vs. Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers),  embedded 3D hybrid integration (of  VCSEL, driver, serializer, polymer waveguide, etc.), 3D CIS/IC integration, and 3D MEMS/IC integration will be discussed in this presentation. Emphasis is placed on various FOWLP assembly methods such as chip-first with die-up, chip-first with die-down, and chip-last (RDL-first). Since RDLs (redistribution layers) play an integral part of FOWLP, various RDL fabrication methods such as Cu damascene, polymer, and PCB (printed circuit board) will be discussed. A few notes and recommendations on wafer vs. panel, dielectric materials, and molding materials will be provided. Also, TSV-less interposers such as those given by Xilinx/SPIL, Amkor, SPIL/Xilinx, ASE, MediaTek, Intel, ITRI, Shinko, Cisco/eSilicon, SONY’s CIS, and Samsung will also be discussed. Furthermore, new trends in semiconductor packaging will be presented.

BRIEF BIO

    With more than 37 years of R&D and manufacturing experience in semiconductor packaging, John has published more than 440 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks on, e.g., Advanced MEMS Packaging (McGraw-Hill Book Company, 2010), Reliability of RoHS compliant 2D and 3D IC Interconnects (McGraw-Hill Book Company, 2011), TSV for 3D Integration, (McGraw-Hill Book Company, 2013), and 3D IC Integration and Packaging (McGraw-Hill Book Company, 2016). John is an elected ASME Fellow and has been an IEEE Fellow since 1994.   

CONTENTS

(A)  Introduction

(B)  Fan-Out Wafer/Panel-Level Packaging

(1) Patents Impacting the Semiconductor Packaging

(2) Fan-out Wafer/Panel-Level Packaging Formations

Ø Chip-first (die-down)

Ø Chip-first (die-up)

Ø Chip-last (RDL-first)

(3) RDL Fabrications

Ø Polymer method

Ø PCB/LDI method

Ø Cu damascene method

(4) TSMC InFO-WLP

(5) TSMC InFO-PoP vs. Samsung ePoP

(6) Wafer vs. Panel Carriers

(7) Notes on Dielectric and Epoxy Mold Compound

(8) Semiconductor and Packaging for IoTs (SiP)

(9) Wafer/Panel-Level System-in-Package (WLSiP and PLSiP)

(10) Package-Free LED (Embedded LED CSP)

 (C) 3D IC Integration with TSVs

  (1) Memory Chip Stacking – Samsung’s DDR4

  (2) Hybrid Memory Cube (HMC) – Micron/Intel’s Knights Landing

  (3) High Bandwidth Memory (HBM) – Hynix/AMD’s and Samsung/Nvidia’s GPU

  (4) Chip stacking by TCNCF

  (5) Samsung’s Widcon

   (6) 3D IC/MEMS Integration

   (7) 3D IC/CIS Integration

    (8) Embedded 3D Hybrid Integration

    (D) 2.5D IC Integration and TSV-Less Interposers

     (1) TSMC/Xilinx’s CoWoS

     (2) Xilinx/SPIL’s TSV-less SLIT

     (3) SPIL/Xilinx’s TSV-less NTI

     (4) Amkor’s TSV-less SLIM

     (5) ASE’s TSV-less FOCoS

     (6) MediaTek’s TSV-less RDLs by FOWLP

      (7) Intel’s TSV-less EMIB

      (8) ITRI’s TSV-less TSH

      (9) Shinko’s TSV-less i-THOP

      (10) Cisco/eSilicon’s TSV-less Organic Interposer

      (11) Samsung’s TSV-less Organic Interposer

      (12) SONY’s TSV-less CIS

       (E) Semiconductor Packaging New Trends

       (F) Summary and Q&A